This invention relates to a method for forming a wiring pattern of a semiconductor device of a dual damascene structure.
As the density of a semiconductor integrated circuit increases, a manufacturing technique of a semiconductor device having a multilayer structure has been rapidly developed. In order to manufacture the semiconductor device having the multilayer structure, it is necessary to form a trench wiring for connecting respective elements arranged along a horizontal direction and a via-hole wiring for connecting respective elements arranged along a vertical direction. Recently, a semiconductor element having a dual damascene structure has been widely used, in which the trench wiring and the via-hole wiring are formed at the same time. In the manufacturing of the dual damascene structure, a pattern of a hard mask (such as SiO2 layer) is formed, and an insulation film (such as Low-k layer) having low dielectric constant is etched via the hard mask to thereby form a trench and a via-hole. Then, wirings are formed in the trench and the via-hole using a material (such as Cu) that has high vapor pressure and does not easily form compound.
In the above described prior art, in a step in which a hard mask is exposed, a corner (i.e., a shoulder) of the hard mask tends be grounded and tapered, i.e., a faceting (i.e., a shoulder sag) tends to occur. In order to prevent the faceting of the hard mask, there is proposed anther method for forming the dual damascene structure. In this method, a trench-formation resist is coated on the hard mask, and the hard mask is patterned by means of photolithography using the trench-formation resist and is etched. Then, a via-formation resist is coated on the hard mask, and the hard mask is patterned by means of photolithography using the via-formation resist and is etched (see, for example, Patent Document No. 1). Further, there is proposed another method for forming a dual damascene structure using a photomask having a gray scale (see, for example, Patent Document No. 2).
Patent Document No. 1: Japanese Laid-open Patent Publication No. 2002-124568.
Patent Document No. 2: Japanese Patent Publication No. 3117886.
However, a method disclosed in the Patent Document No. 1 includes two photolithographic steps and two etching steps. Therefore, the manufacturing process may become complicated, and the patterning accuracy may be reduced.
Further, in a method disclosed in the Patent Document No. 2, a minimum pitch, minimum dimension and minimum step size of a mask pattern are limited by the resolution and the dimension controllability in the manufacturing process of the photomask, and are subject to applicable lower limits. Furthermore, in the case where a highly accurate manufacturing process of the photomask is employed, there is a problem that the manufacturing cost of the photomask increases, and therefore a practical dual damascene structure can not be obtained.